Driving of loads by the Pulse Width Modulation (PWM) procedure through output stages consisting of bridge circuits is a fairly widespread practice in various electrical systems and in particular for direct current spindle motors and direct current voice coil motors. It is often useful to be able to control not only the intensity but also the direction of the current supplied to the load by the bridge circuit.
A complete collection of articles on this subject can be found in the catalog of SGS-THOMSON MICROELECTRONICS, "Designers' Guide to Power Products", June 1992 version, in the chapter entitled "DC and Brushless Motors".
A simplified diagram of a bridge circuit is shown in FIG. 1. The bridge circuit includes two terminals I1 and I2 for a signal input, two terminals O1 and O2 for a signal output, and two terminals C1 and C2 for control inputs. The main conduction paths, i.e., drain-source, of four n-channel MOS transistors T1, T2, T3 and T4 constitute the branches of the bridge circuit. The control terminal of transistors T1 and T3 are connected directly to the terminals C1 and C2, respectively. The control terminal of the transistor T2 is connected to the terminal C1 through an inverter P1. The control terminal of the transistor T4 is connected to the terminal C2 through an inverter P2. A load LD, represented by a motor symbol but not part of the bridge circuit, is shown between the terminals O1 and O2 in FIG. 1.
Typically, terminal I1 is coupled to a power potential reference VDD and terminal I2 is coupled to a ground potential reference GND as shown in FIG. 2.
If the potential at the terminal C1 is high, the transistor T1 is on and the transistor T2 is off. If the potential at the terminal C1 is low, the transistor T1 is off and the transistor T2 is on. All this applies similarly for the terminal C2 and the transistors T3 and T4.
By applying appropriately conduction control signals to the terminals C1 and C2 there can be obtained at the output O1-O2 a voltage signal having a virtually square wave form with a duty cycle such that the average current flowing in the load connected to the output O1-O2 of the bridge circuit assumes the desired value.
A simple and known way to drive the control inputs C1 and C2 of the bridge circuit is to send to one of the inputs, e.g., C1, a first voltage conduction control signal having a constant value and to the other input, e.g., C2, a second voltage conduction control signal consisting of a virtually square wave. By controlling the duty cycle of this second signal one controls the duty cycle of the output O1-O2 and consequently the intensity of the average current in the load LD. When it is desired to obtain an average current of the same intensity but opposite direction it suffices to send the first signal to the input C2 and the second signal to the input C1.
FIG. 2 shows a bridge circuit BR, similar to the bridge circuit shown in FIG. 1, having input terminal I1 connected to the reference VDD and input terminal I2 coupled to the reference GND in combination with a driving circuit. The driving circuit includes an oscillator OS0 designed to generate square waves with fixed frequency and duty cycle at one of its outputs. A resistor RS for detection only of the current module is connected between the terminal I2 and the reference GND. A comparator CO0 has a non-inverting input connected to the resistor RS and an inverting input receiving a reference signal VR corresponding to the desired current at the output O1-O2. A flip-flop FF of the SR type has a set terminal S connected to the output of the oscillator OS0 and reset terminal R connected to an output of the comparator CO0. Two AND logical gates G1 and G2 have first inputs connected together to a state output Q of the flip-flop FF and second inputs receiving respectively two logical signals L1 and L2, one inverted with respect to the other.
The circuit of FIG. 2 operates in accordance with the structure just described. Indeed, one of the signals L1 and L2 will necessarily have a low logical value and thus the output of the AND logical gate to which it is connected will have a low logical value regardless of the logical value of the output Q. During constant frequency operation, a square wave with constant frequency and constant average duty (cycle is linked to the value of the signal VR and will be present at the output Q. A similar effect would be obtained in the circuit of FIG. 2 when the oscillator OS0 and the flip-flop FF are replaced with a monostable circuit started by the output of the comparator CO0. At operating condition however, the output of the monostable would provide a square wave with constant average frequency and constant average duty cycle. This is constant off time (Toff) operation.
Such a circuit exhibits a lower intrinsic limit for the controllable current. Additionally, the duty cycle of the wave at the output Q cannot decrease continuously to zero. Even if it were possible to control the duty cycle of this square wave to very low values, the bridge BR could not respond adequately to very short pulses. Therefore if it is desired to regulate the current in the load LD in an interval comprising both negative and positive values, the linearity of the regulation would be irreparably endangered around the null current values and in addition appropriate circuitry would be necessary to generate the signals L1 and L2.